x86/AMD: Do not intercept access to performance counters MSRs
authorBoris Ostrovsky <boris.ostrovsky@oracle.com>
Mon, 15 Apr 2013 09:24:27 +0000 (11:24 +0200)
committerJan Beulich <jbeulich@suse.com>
Mon, 15 Apr 2013 09:24:27 +0000 (11:24 +0200)
commit45773c5fb6346b1bc2a2ddcc6d19bd7f53ccabff
tree027ff8787a8cdcd90c85834fe07d646105b8a91b
parent6f3c6d1ed8d2c8b6cd5d9689159e3647bf428dcd
x86/AMD: Do not intercept access to performance counters MSRs

Access to performance counters and reads of event selects don't
need to always be intercepted.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
xen/arch/x86/hvm/svm/svm.c
xen/arch/x86/hvm/svm/vpmu.c